L&T Technology Services Limited

CA, US

Systems Engineer V-2961-1

L&T Technology Services Limited (LTTS) is a listed subsidiary of Larsen & Toubro Limited focused on Engineering and R&D (ER&D) services. We offer consultancy, design, development and testing services across the product and process development life cycle. Our customer base includes 52 Fortune 500 companies and 51 of the world’s top ER&D companies, across industrial products, medical devices, transportation, telecom & hi-tech, and the process industries. Headquartered in India, we have over 14,700 employees spread across 17 global design centers, 27 global sales offices and 48 innovation labs as of December 31, 2018. For additional information about L&T Technology Services log on to [ Link Removed ]



  • Writing C/C++ System Level tests targeting the CPU/DSP/CNN cores in CPP
  • Writing C/C++ Performance and Power system-level use-cases
  • Work on FPGA and Emulation scripts and flows for system validation, to increase productivity across the team
  • Work on post-silicon bringup and flows
  • Work closely with Algorithm engineers, DV engineers, Architects and Designers to come up with system level use-case scenarios
  • Work closely with Design Verification to enhance and augment verification for IPs on FPGA and/or Emulation platforms
  • Work closely with Firmware, Reference Modeling, and Software engineers to assist software development and debug

What are the must have non-negotiable requirements for this role?

  • Experience in C/C++ for writing system level test-cases for SoC like IP
  • Experience in scripting languages such as Python, TCL etc
  • Experience running tests on FPGA and/or Emulation platforms for SoC like IP
  • Experience in post-silicon bringup and flows for SoC like IP
  • Experience with lab system debug with logic analyzers, scopes, meters, etc
  • Experience in performance evaluation and modeling for SoC like IP
  • Experience in power tests and evaluation on prototyping platforms
  • Familiarity with AMBA protocol, OCP protocol
  • Familiarity in System Verilog for design and verification - for debugging

**IMPORTANT Q&A**

  • Is this an FPGA, SOC FPGA or SOC ASIC project?
    SOC ASIC target, but we are using a FPGA and Emulator, for silicon verification/validation.
  • Does the engineer need to contribute in the design (RTL, synthesis), verification (SV/UVM or similar) or validation (post-si testing and system enabling) areas?
    Verification - writing system-level tests running on the CPU and/or DSP which run on FPGA/Emulator.
  • Is a hardware (either RTL or Verification) or a firmware / software (system software/firmware, drivers) background a closer fit to the project’s needs?
    A mix - since it's pre-silicon verification, writing FW like tests, for system level validation.
    Skills
  • What are the nice to have details for this role?
    • Performance modeling and evaluation
    • Knowledge of OS kernel and experience in driver development
    • Familiarity with IO’s such as MIPI CSI & DSI, USB, PCIE, LPDDR